This invention relates to apparatus and methodology which facilitates interaction among central processing units (CPUs) in a multiprocessing system in the control of page frames. The invention enables each CPU to complete its current use of operands in a page frame even though the page frame has been marked by another CPU in the multiprocessing system as not available for subsequent use. The invention does this by maintaining the addressability to each required page frame for the duration of each instruction regardless of any changes in the translation tables in storage and regardless of any changes in the translation lookaside buffer during that instruction.
The invention can be applied where plural CPUs independently contend for main store resources in a multiprocessing system using demand-paging and virtual storage operations. A page frame is a hardware component of main store in which a page can be copied from an I/O device. The number of page frame components in a main store are limited. Whenever an operand is required by the current instruction in any CPU, and the operand is not in main store, a page-demand interrupt is generated by the CPU so that the system can transfer the page containing the operand from an I/O device into a page frame component in main store. If all page frame components are then in use, the system can deallocate one of the page frames and reallocate it for the new page having the required operand. The deallocated page may also have been used by one or more other CPUs. If the deallocation occurs in the middle of execution of a current instruction in another CPU having incomplete results obtained thus far, a cessation of execution for that instruction may leave incorrect results. In this manner, incorrect data may be provided in a CPU output, due to the asynchronous interference of CPUs in the multiprocessing system. Furthermore if the system should recognize the incomplete execution, and later retry the instruction after the page is again brought back into main store, a reduction in efficiency occurs for the multiprocessing system due to the thrashing of this page in regard to the instruction suppressed at some intermediate point in its execution.